Wafer-scale membrane release process
manufacturing
Wafer-scale membrane release process (GSC-TOPS-231)
This innovation consists of a process of fabricating thin dielectric membranes constructed with a silicon-on-insulator wafer material.
Overview
Precise measurements utilizing sensitive instruments may require thermally managed detectors. Therefore, thermal insulation of the detector is essential to its performance. To maintain critical signal to noise ratio, there is a need for larger thermal isolation structures. Due to high detector filling fraction limits, these isolation structures may be thinner, less mechanically robust thermal and more prone to breakage during fabrication. This innovation is a process that fabricates thin dielectric membranes with high mechanical yields. These dielectric membranes may be perforated and include thermal isolation structures.
The Technology
The process of forming thermal insulation wafer begins with layering a photo resist pattern on an aluminum coated substrate. After the aluminum is etched, a temporary adhesive is applied to the photo resist and substrate. Next, the construction undergoes wafer scale bonding to a silicon insulator. The silicon insulator is then patterned and etched down to the buried oxide layer. The temporary adhesive is then dissolved in acetone. The acetone is diluted with non-polar solvents which are then removed via critical drying.
Goddard Space Flight Center has produced multiple arrays of crystalline silicon membranes that were 450 nm thick and were isolated from a silicon support structure by thermal isolation structures that were 30 microns thick and 5 microns long. The largest membranes, among which had 100 % mechanical yield, had an aerial footprint of 1.6 mm x 1.4 mm.
Benefits
- Large mechanical yield
- Minimizes wafer handling
Applications
- Bolometric detectors
- Thermally insulated sensors
Technology Details
manufacturing
GSC-TOPS-231
GSC-17897-1
