Simplified Complimentary Metal-oxide-semiconductor Manufacturing Technique

manufacturing
Simplified Complimentary Metal-oxide-semiconductor Manufacturing Technique (LAR-TOPS-304)
Unique deposition process for CMOS manufacturing eliminating photoresists, UV exposure and other steps - Applicable for 3D transistors
Overview
Current microfabrication methods are well established for processing of Si-based complementary metal-oxide-semiconductor (CMOS) and only get more complex with each iteration. This is especially true with 3D transistors that require very selective placement and selective removal of materials required to reach a working product. However, with NASA's newly developed masking and deposition processes, photoresists, UV exposures and selective etching can be eliminated, with metal removal reduced to only planarization. This revised process reduces the total material and time requirements drastically when compared to current standards. These advancements offer the benefits of increasing total possible throughput while simultaneously reducing manufacturing cost per unit.

The Technology
This innovation represents an alternative method to skip several of the conventional fabrication steps, using a mask designed to allow molecules in a sputtering plume to pass through openings engineered in the mask. This causes material to go where desired, without photoresist, and without selective etching, thus simplifying the process, reducing cost, chemical waste; and increasing throughput. This method masks areas that do not need deposited material, causing local deposition instead. The shape and size are within tolerance. No etching steps, no photoresist patterning, and no metal removal is necessary. Other than planarization, selective deposition has replaced every step in the conventional process, accomplishing the same result in 8 steps instead of 19. The technology can be easily used to fabricate custom chips and specialized sensors and devices that use the group III-V and II - VI semiconductor materials.
Comparison of the conventional & new processes. Image Credit: NASA
Benefits
  • Shortens the patterning process for deposition, skipping the need for photoresist and UV exposure
  • Cost is reduced
  • Environmental impact is reduced from less chemical disposal
  • Less material waste from etching away undesirable deposition
  • Most effective for fabrication process for group III-V and II-VI semiconductors which do not have proper gate oxides
  • Effective for thick film processing

Applications
  • Semiconductors
  • Computer equipment
  • Telecommunications equipment
  • Wireless communications
  • Automotive applications
  • Electronic imaging / optoelectronics
  • Medical imaging
Technology Details

manufacturing
LAR-TOPS-304
LAR-18925-1
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