Improved Indium Bump Bonding Using Multi-Step Plasma Process

To avoid catastrophic failure, traditional electrical ohmic contacts must be placed at some distance from the optimal position (especially for sensors) in high-temperature environments. In addition, conventional metallization techniques incur significant production costs because they require multiple process steps of successive depositions, photolithography, and etchings to deposit the desired ohmic contact material. Glenn's novel production method both produces ohmic contacts that can withstand higher temperatures than ever before (up to 600°C), and permits universal and simultaneous ohmic contacts on n- and p-type surfaces. This makes fabrication much less time-consuming and expensive while also increasing yield. This innovative approach uses a single alloy conductor to form simultaneous ohmic contacts to n- and p-type 4H-SiC semiconductor. The single alloy conductor also forms an effective diffusion barrier against gold and oxygen at temperatures as high as 800°C. Glenn's extraordinary method enables a faster and less costly means of producing SiC-based sensors and other devices that provide quicker response times and more accurate readings for numerous applications, from jet engines to down-hole drilling, and from automotive engines to space exploration.

NASA Glenn's durable, extreme-temperature, integrated circuit chips begin with the replacement of conventional silicon IC transistors with n-channel SiC junction field effect transistors (JFET) and resistors that can reliably function above 500°C. JFETs with the necessary high-temperature stability and electrical gain are fabricated from commercial 4H-SiC wafers with epilayers using dry etching and a self-aligned n-type ion implantation. An innovative circuit approach creates digital logic gates from these normally-on n-channel JFETs and resistors. Using two levels of 500°C durable metal to interconnect numerous SiC gates, complex circuits enabling a variety of control, operation and sensing functions for intelligent systems in harsh environments can be implemented in physically small chips. The challenge of getting electrical signals to and from the chip in a harsh environment is overcome by the use of the iridium interfacial stack (IrIS) that acts simultaneously as a bond metal and diffusion barrier, and can be used on an ohmic contact to the SiC. Combined with Glenn-developed high-temperature durable ceramic chip packaging and harsh environment sensor technology, this revolutionary durable integrated circuit technology is game changing for harsh-environment applications of all types.

The interlayer consists of lithiophilic metallic or metal-containing nanoparticles supported on holey graphene, a special carbon material perforated by small holes that enables dry processing. The composite interlayer guides uniform lithium deposition and maintain stability during cycling. The result is a thin, film-like material that can be integrated (via dry processes) into battery cells as standalone interlayers or combined with solid electrolyte and cathode powders to form bi- and tri-layer structures, separating anodes and electrolytes while encouraging efficient ionic movement and long cell lifecycles. Tests found that battery cells incorporating this dry-processed interlayer achieved ultrahigh current density and low overpotential, indicating that the interlayer prevents rough patches, resists dendrite formation, and supports efficient charge and discharge over time. The interlayer has demonstrated a high lithium-ion flux (i.e., a high critical current density of ~25 mA/cm²) and has shown that full battery cells incorporating the protective layer can be successfully cycled (with an areal capacity of 7 mAh/cm²). This innovation contributes to both the SABERS (LEW-TOPS-167) and SABERS 2.0 (LEW-TOPS-188) portfolios, improving the state of the art for solid state batteries. The anode interlayer is currently at a TRL 4 and is available to license independently or as part of the larger SABERS solid-state battery suite.

The technology is an innovative process for creating metal-patterned, structured membranes for micromachining applications. The method uses potassium hydroxide to remove silicon, in combination with XHRiC. Hafnium metal is first patterned onto a silicon nitride wafer, which serves as the starting substrate. XHRiC is then applied to the wafer, followed by patterning with photoresist and etching using O2 plasma to define cut slots in the membrane. The photoresist is then removed. Next, the wafer is bonded to a Pyrex carrier wafer with wax, and the backside of the silicon nitride is patterned and reactive-ion etched. The wafer is then placed in hot potassium hydroxide for 16 hours to remove the silicon layer, creating a silicon nitride membrane. The wafer is subsequently placed in acetone to dissolve the wax. The wafer is resecured to the Pyrex carrier wafer, and the topside of the silicon nitride membrane is subjected to reactive-ion etching. Finally, the XHRiC layer is removed using O2 plasma, and the Pyrex handle wafer is released, resulting in a metal-patterned silicon nitride membrane with cut slots. This novel process supports the creation of structured membranes with a wide range of applications in MEMS fabrication. The use of XHRiC as a patterned hard mask and/or etch protection material enables its application in various MEMS devices. The process can be used to fabricate cut membranes, micro/nano structures, and ultra-thin films for device applications, making it an excellent candidate for MEMS foundry companies and accelerometer manufacturers. It has reached a Technology Readiness Level (TRL) 5 (component validation in a relevant environment) and is now available for patent licensing.

This innovation represents an alternative method to skip several of the conventional fabrication steps, using a mask designed to allow molecules in a sputtering plume to pass through openings engineered in the mask. This causes material to go where desired, without photoresist, and without selective etching, thus simplifying the process, reducing cost, chemical waste; and increasing throughput. This method masks areas that do not need deposited material, causing local deposition instead. The shape and size are within tolerance. No etching steps, no photoresist patterning, and no metal removal is necessary. Other than planarization, selective deposition has replaced every step in the conventional process, accomplishing the same result in 8 steps instead of 19. The technology can be easily used to fabricate custom chips and specialized sensors and devices that use the group III-V and II - VI semiconductor materials.