Atomic Layer Deposition Chamber for Automated Semiconductor Processing Equipment
Manufacturing
Atomic Layer Deposition Chamber for Automated Semiconductor Processing Equipment (NPO-TOPS-49)
Reduces sample contamination, lowers costs, and integrates with host systems
Overview
Researchers at NASA's Jet Propulsion Laboratory (JPL) have designed a novel atomic layer deposition (ALD) chamber that enables integration with a molecular beam epitaxy (MBE) system in an unbroken vacuum system. This novel innovation supports automated sample transfer and highly automated semiconductor processing equipment.
JPL's ALD chamber design offers a variable volume and can be configured to process wafers in a facedown orientation. These key features reduce chip processing costs and allow wafers to be processed in the same orientation as in MBE and other host systems. Encapsulating the ALD and MBE systems in a single vacuum system eliminates exposure to the atmosphere and significantly reduces contamination risks.
The Technology
Researchers at JPL have redesigned a typical standalone ALD chamber in a way that is fully compatible with automated semiconductor processing systems, yet maintains the benefits of a conventional ALD chamber—a small-volume reaction chamber, heated sample holders, and laminar gas flow.
The unique three-part ALD chamber incorporates the heater, sample transfer mechanism, and laminar gas injectors into a collapsing pancake design, which enables self-assembly within the reaction chamber. The design utilizes a facedown sample arrangement, which reduces particulate contamination compared to standard faceup ALD systems. Integration with the MBE system also ensures that the ALD chamber remains clean and contaminant-free compared with conventional shared-use, standalone ALD systems. Further, the chamber is engineered to use the fewest number of actuators and provide the greatest design flexibility for all types of host systems and ALD processes.
Because no automated system currently exists that incorporates both MBE and ALD processes in one unbroken vacuum system, atmosphere exposure is unavoidable when transferring components for processing. Encapsulating ALD and MBE processing chambers offers a significant process improvement and reduces the cost of producing components with precise MBE films. This innovation is anticipated to add great value to advanced image detector processing at JPL, as well as to the semiconductor industry.
Originally developed for specific use with a JPL-developed MBE system, this innovation would be useful for any semiconductor industry customer seeking to prevent atmosphere exposure to MBE films prior to ALD processing in an automated system.
Benefits
- Lower cost: Microencapsulation allows smaller amounts of precursor materials to be used
- Automated transfer: Components are oriented in the same direction to allow for automated sample transfer between processing chambers
- Flexible: Integrates easily with existing host systems
- Enhanced cleanliness: Reduces sample contamination risk due to facedown orientation and intra-vacuum integration with host systems
Applications
- Semiconductor processing
- Nanotechnology
- Spin transport electronics
- Advanced image detectors
Technology Details
Manufacturing
NPO-TOPS-49
NPO-49739-1
Patent Pending
Patent Pending
Similar Results
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Epitaxy of SiGe and Other Compound Semiconductors
Several of the patented methods included in this suite of technologies enable super-hetero-epitaxy of rhombohedral/cubic compound semiconductors on specially oriented trigonal (e.g. sapphire) or hexagonal (e.g. quartz) crystal wafer substrates. This includes alignment of the growth crystal lattice with the underlying substrate lattice to minimize misfit strain-induced dislocation defects in the growing crystal. Thus thicker, defect-free crystal layers can be made. Rhombohedral/Cubic crystal twin defects which is 60 degree rotated on [111] orientation in a rhombohedral/cubic SiGe layer structure can be reduced to well less than 1% by volume, essentially providing a defect-free semiconductor material. Alternately, engineered lattice structures with a high degree of twinning can provide SiGe with improved thermoelectric properties due to the phonon scattering that inhibits thermal conduction without compromising electrical conductivity. Additional patented technologies in this suite provide for physical vapor deposition (PVD) growth methods utilizing molten sputtering targets and thermal control of heated substrates, including electron beam heating, in order to give the atoms in the sputtered vapor or on the substrate surface the energy needed for the desired crystal growth.
The remaining patented technologies enable x-ray diffraction methods for detecting and mapping crystal twin defects across the entire as-grown semiconductor layer. These defects are critical to the performance of any semiconductor device manufactured from such compound semiconductor materials.
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Low-Cost Detection of Thin Film Stress during Fabrication
Traditional methods of determining film stress use ex-situ deflectometry techniques and require significant and costly modifications to the vacuum chamber to allow optical access to the substrate. These techniques determine film stress by measuring the change in substrate curvature resulting from stress.
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