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The technology is an all-printed Physically Unclonable Function (PUF) electronic device based on a nanomaterial (such as single-walled carbon nanotube) network. The network may be a mixture of semiconducting and metallic nanotubes randomly tangled with each other through the printing process. The all-printed PUF electronic device comprises a nanomaterial ink that is inkjet deposited, dried, and randomly tangled on a substrate, creating a network. A plurality of electrode pairs is attached to the substrate around the substrate perimeter. Each nanotube in the network can be a conduction path between electrode pairs, with the resistance values varying among individual pairs and between networks due to inherent inter-device and intra-device variability. The unique resistance distribution pattern for each network may be visualized using a contour map based on the electrode information, providing a PUF key that is a 2D pattern of analog values. The PUF security keys remain stable and maintain robustness against security attacks. Although local resistance change may occur inside the network (e.g., due to environmental impact), such change has little effect on the overall pattern. In addition, when a network-wide resistance change occurs, all resistances are affected together, so that the unique pattern is maintained.

Next generation instruments are capable of producing data at rates of 108 to 1011 bits per second, and both their instrument designs and mission operations concepts are severely constrained by data rate/volume. SpaceCube is an enabling technology for these next generation missions. SpaceCube has demonstrated enabling capabilities in Earth Science, Planetary, Satellite Servicing, Astrophysics and Heliophysics prototype applications such as on-board product generation, intelligent data volume reduction, autonomous docking/landing, direct broadcast products, and data driven processing with the ability to autonomously detect and react to events. SpaceCube systems are currently being developed and proposed for platforms from small CubeSats to larger scale experiments on the ISS and standalone free-flyer missions, and are an ideal fit for cost constrained next generation applications due to the tremendous flexibility (both functional and interface compatibility) provided by the SpaceCube system.

NASA Glenn's durable, extreme-temperature, integrated circuit chips begin with the replacement of conventional silicon IC transistors with n-channel SiC junction field effect transistors (JFET) and resistors that can reliably function above 500°C. JFETs with the necessary high-temperature stability and electrical gain are fabricated from commercial 4H-SiC wafers with epilayers using dry etching and a self-aligned n-type ion implantation. An innovative circuit approach creates digital logic gates from these normally-on n-channel JFETs and resistors. Using two levels of 500°C durable metal to interconnect numerous SiC gates, complex circuits enabling a variety of control, operation and sensing functions for intelligent systems in harsh environments can be implemented in physically small chips. The challenge of getting electrical signals to and from the chip in a harsh environment is overcome by the use of the iridium interfacial stack (IrIS) that acts simultaneously as a bond metal and diffusion barrier, and can be used on an ohmic contact to the SiC. Combined with Glenn-developed high-temperature durable ceramic chip packaging and harsh environment sensor technology, this revolutionary durable integrated circuit technology is game changing for harsh-environment applications of all types.

Electronic waveforms exist that exceed the capabilities of state-of-the-art data acquisition hardware that is commonly available. The electronic waveforms that need to be measured simultaneously contain wide bandwidth, high frequency content, a DC reference, high dynamic range, and a high crest factor. The NASA Glenn high-speed data acquisition system creates a voltage compression effect with a custom transfer function that is adapted to the voltage range, frequency bandwidth, and electrical impedance of both the test article and data acquisition device. The compression transfer function is later reversed (or decompressed) with a software algorithm to restore the original signal's voltage from the acquired data. The data is thus improved via better signal-to-noise ratio, better low-amplitude accuracy, better resolution, and preservation of high-frequency spectral content. The circuit can be realized with either passive components or both active and passive components. Either realization is specialized for the test article and data acquisition hardware. This is an early-stage technology requiring additional development. Glenn welcomes co-development opportunities.

To avoid catastrophic failure, traditional electrical ohmic contacts must be placed at some distance from the optimal position (especially for sensors) in high-temperature environments. In addition, conventional metallization techniques incur significant production costs because they require multiple process steps of successive depositions, photolithography, and etchings to deposit the desired ohmic contact material. Glenn's novel production method both produces ohmic contacts that can withstand higher temperatures than ever before (up to 600°C), and permits universal and simultaneous ohmic contacts on n- and p-type surfaces. This makes fabrication much less time-consuming and expensive while also increasing yield. This innovative approach uses a single alloy conductor to form simultaneous ohmic contacts to n- and p-type 4H-SiC semiconductor. The single alloy conductor also forms an effective diffusion barrier against gold and oxygen at temperatures as high as 800°C. Glenn's extraordinary method enables a faster and less costly means of producing SiC-based sensors and other devices that provide quicker response times and more accurate readings for numerous applications, from jet engines to down-hole drilling, and from automotive engines to space exploration.

A prototype device has been developed at Glenn for creating shapes from SMA wire. The apparatus uses material feedstock in spools made of alloys that exhibit the shape memory effect (temperature-induced activation), super elasticity (stress-induced activation), and to some extent, magnetism (magnetically-induced activation). The feedstock (e.g., wire spool) is routed and positioned around a series of modular pins to create a shape outline. Once the desired shape is formed, the wire ends are clipped from the feedstock and secured into a locking mechanism, then connected to a heating circuit (e.g., joule heating, hot plate, heat gun). The programmable prescribed circuit parameters, including current or temperature and training time, are set and confirmed using the apparatus control dials and indicators to ensure safe and accurate operation of the device. Before enabling the circuit, a plastic shield is placed over the modular array to protect the operator. The final product will be a desired shape that can be deformed and recovered numerous times through heat activation.

Combining a dynamic load emulation technique with a PWM dithering technique, NASA’s technology provides a more efficient, cost-effective, and practical method to emulate complex loads. While there are commercially available electronic device loads on the market that meet basic emulation needs, these devices are limited; they are limited with respect to small input voltage changes, and to feedback signals from the device’s power system, which may lack the strength and resolution needed to emulate accurately. A common solution for the bus emulation limitation is to construct a model of an actual microgrid using representative loads and connections. But this can be complex, costly, and have limitations in performance. NASA’s approach addresses these challenges without creating an actual model microgrid to replicate the systems. As opposed to stand-alone COTS electronic load devices or model microgrids using representative loads and connections for a given test, NASA’s technology is a system constructed of an input power filter, a COTS electronic load device or load subsystem, and a power control circuit. The input power filter is designed to emulate load or bus performance at the medium to high frequency range. The power control circuit combined with the electronic load or load subsystem emulates lower frequency and constant power dynamics of the system. Lastly, the power control circuit linearizes digitization and quantization issues present with digitally controlled COTS electronic loads. The power control circuit can be set to measure a load voltage, which is divided by a determined value for power, and combined with a triangle wave dither (the power control circuit block image demonstrates how to integrate a triangle wave dither). This dither dynamically adjusts the electrical current or power to keep it constant within the commercially purchased load device, enabling accurate emulation of complex DC microgrid systems.

The technology is part of a new generation of NASA Glenn SiC integrated circuits with unprecedented durability in the field of high-temperature electronics. For robust operational amplifiers based on SiC Junction Field Effect Transistors (JFETs), this novel compensation method mitigates issues with threshold voltage variations that are an effect of die location on the wafer. Modern high-temperature op amps on the market fall short due to temperature limits (only 225°C for silicon-based devices). Previously, researchers noted that multiple op amps on a single SiC wafer had different amplification properties due to different threshold voltages that varied spatially as much as 18&#37 depending on the circuit's distance from the SiC wafer center. While 18&#37 is okay for some applications, other important system applications demand better precision. By applying this technology to the amplifier circuit design process, the op amp will provide the same signal gain no matter its position on the wafer. The compensation approach enables practical signal conditioning that works from 25°C up to 500°C.

The prior art offers a variety of thermal blocking filter construction techniques and designs. In the devices most basic form, a large shunt capacitor forms a single-pole low-pass-filter. More generally, multiple low-pass lumped element stages can be combined in series to produce compact and broadband non-dissipative filter structures. The challenges presented by these implementations include controlling inter-stage isolation and spurious transmission resonances, limiting the filters total shunt capacitance, and achieving adequate control over circuit parameters as a function of temperature. In this work, simple matched filter designs based on easily realized absorptive dielectric transmission lines are improved upon. Innovators at NASA Goddard Space Flight Center have designed, fabricated, and characterized absorptive thermal blocking filters for cryogenic microwave applications. The device allows direct integration of the high frequency signal and microwave readout and mitigates spurious resonances in the circuit response. This leads to improved electrical performance and a reduction in the required circuit area. The transmission line filters input characteristic impedance is designed to match 50 ohms and its response has been validated from 0 to 50 GHz. The observed return loss in the 0 to 20 GHz design band is greater than 20 dB and shows graceful degradation with frequency. The filters response is calculable, repeatable under cryogenic cycling, and is capable of providing an intrinsically broadband matched impedance termination. This technology is generally applicable in the realm of high frequency circuits, is scalable and can be modified for use in other applications.