Electrical and Electronics

PATENT PORTFOLIO
Electrical and Electronics
Electrical and Electronics
The scientific and technological development, behavior and application of electronic devices, circuits and systems involving the flow of electrons in semiconductors, gaseous media or a vacuum.
Jet Turbine Profile
Packaging for SiC Sensors and Electronics
Prior approaches to bonding a SiC sensor and a SiC cover member relied on either electrostatic bonding or direct bonding using glass frits. The problem with the former is that its relatively weak bond strength may lead to debonding during thermal cycling, while the latter requires the creation of apertures that can allow sealant to leak. Glenn's innovation uses NASA's microelectromechanical system direct chip attach (MEMS-DCA) technology that can be bulk-manufactured to reduce sensor costs. The MEMS-DCA process allows a direct connection to be made between chip and pins, thereby eliminating wire bonding. Sensors and electronics are attached in a single-stage process to a multifunctional package, which, unlike previous systems, can be directly inserted into the housing. Additional thick pins within the electrical outlet allow the package to be connected to external circuitry. Furthermore, because the top and bottom substrates' thermomechanical properties are similar to that of the sensors, the problem of mismatch in the coefficient of thermal expansion is significantly reduced, minimizing thermal cycling and component fatigue. By protecting sensors and electronics in temperatures up to 600°C, approximately twice what has previously been achievable, Glenn's innovation enables SiC components to realize one of their most exciting possibilities - direct placement within high-temperature environments.
NASA Goddard Space Flight Center Webb Instruments Perfected to Microscopic Levels
Custom Application Specific Integrated Circuit for Detector Control and Data Acquisition
The ASIC receives signals from the detector via an analog-to digital converter (ADC). This ADC includes a full analog front-end with signal routing and pre-amplification. The digital signals are then routed through an Output Data Formatter and are directed to warm electronics. A digital Control component provides clocking for the detector and external serial control. The BIAS component provides quiet voltages to the detector. This electrical architecture minimizes thermal stress loads while maximizing signal integrity. The processing functions are performed at the highest allowable temperatures minimizing the number of components that require cooling.
Supercapacitors
Metal Oxide-Vertical Graphene Hybrid Supercapacitors
The electrodes are soaked in electrolyte, separated by a separator membrane and packaged into a cell assembly to form an electrochemical double layer supercapacitor. Its capacitance can be enhanced by a redox capacitance contribution through additional metal oxide to the porous structure of vertical graphene or coating the vertical graphene with an electrically conducting polymer. Vertical graphene offers high surface area and porosity and does not necessarily have to be grown in a single layer and can consist of two to ten layers. A variety of collector metals can be used, such as silicon, nickel, titanium, copper, germanium, tungsten, tantalum, molybdenum, & stainless steel. Supercapacitors are superior to batteries in that they can provide high power density (in units of kw/kg) and the ability to charge and discharge in a matter of seconds. Aside from its excellent power density, a supercapacitor also has a longer life cycle and can undergo many more charging sequences in its lifespan than batteries. This long life cycle means that supercapacitors last for longer periods of times, which alleviates environmental concerns associated with the disposal of batteries.
Micro-chip
Chip with micro-hotplate for self-healing and sustainable electronics
Heat treatment, also known as annealing, is a common step in the semiconductor fabrication process. A build-up of radiation-induced localized charge within the semiconductor and insulator alters local field distribution, threshold voltage and leakage current. NASA's patent-pending technology implements an annealing process on a system level directly on a chip for annealing defects and improving device performance with heating done in the laboratory. The annealing may be performed inside an oven, or upon a hotplate. A system on microheater provides defect annealing capability for recovering bulk trapped charges and interface states. The healing starts simply by heating the chip in a process that can be compared to that of humans immune system - something capable of detecting and quickly responding to any number of possible assaults in order to keep the larger system working optimally. A microheater is monolithically integrated on the backside of a generic Complementary Metal Oxide Semiconductor (CMOS) chip for an on-chip annealing system (left Figure 1(b)). Compared to a stacked microheater, the monolithic integration reduces the die profile, which accordingly enhances the heating power efficiency and heating/cooling rates, which was verified experimentally and numerically. The self-healing microheater is controlled by a temperature feedback circuit to maintain the desired temperature. All circuits under the treatment are unbiased in order to avoid any side effects on normal devices. A control circuit block is programmed to monitor a device parameter shift such as the threshold voltage on the same chip in order to determine the need for treatment. A control circuit triggers the micro hotplate and senses the temperature to adjust the target temperature and duration. The microheater and the system-on-chip are fabricated separately and stacked into a single package, which can be implemented on any arbitrary commercial-off-the-shelf device as a generic approach.
Circuit Chip
Integrated Circuit Chips
NASA Glenn's durable, extreme-temperature, integrated circuit chips begin with the replacement of conventional silicon IC transistors with n-channel SiC junction field effect transistors (JFET) and resistors that can reliably function above 500°C. JFETs with the necessary high-temperature stability and electrical gain are fabricated from commercial 4H-SiC wafers with epilayers using dry etching and a self-aligned n-type ion implantation. An innovative circuit approach creates digital logic gates from these normally-on n-channel JFETs and resistors. Using two levels of 500°C durable metal to interconnect numerous SiC gates, complex circuits enabling a variety of control, operation and sensing functions for intelligent systems in harsh environments can be implemented in physically small chips. The challenge of getting electrical signals to and from the chip in a harsh environment is overcome by the use of the iridium interfacial stack (IrIS) that acts simultaneously as a bond metal and diffusion barrier, and can be used on an ohmic contact to the SiC. Combined with Glenn-developed high-temperature durable ceramic chip packaging and harsh environment sensor technology, this revolutionary durable integrated circuit technology is game changing for harsh-environment applications of all types.
Fighter Jet
Metallization for SiC Semiconductors
To avoid catastrophic failure, traditional electrical ohmic contacts must be placed at some distance from the optimal position (especially for sensors) in high-temperature environments. In addition, conventional metallization techniques incur significant production costs because they require multiple process steps of successive depositions, photolithography, and etchings to deposit the desired ohmic contact material. Glenn's novel production method both produces ohmic contacts that can withstand higher temperatures than ever before (up to 600°C), and permits universal and simultaneous ohmic contacts on n- and p-type surfaces. This makes fabrication much less time-consuming and expensive while also increasing yield. This innovative approach uses a single alloy conductor to form simultaneous ohmic contacts to n- and p-type 4H-SiC semiconductor. The single alloy conductor also forms an effective diffusion barrier against gold and oxygen at temperatures as high as 800°C. Glenn's extraordinary method enables a faster and less costly means of producing SiC-based sensors and other devices that provide quicker response times and more accurate readings for numerous applications, from jet engines to down-hole drilling, and from automotive engines to space exploration.
front image
Digital Machine Control Electronics
The SCAPS (Single-Coil Absolute Position Sensor) GAPSYN (Inductive Gap Sensor) Digital Signal Conditioning Electronics technology (MFS-32318-1) provides voltage that is proportional to the position of the sensor. This circuit processes two signals from the position sensor to determine the amplitude of an amplitude-modulated signal from the position sensor, correcting for gap fluctuations and nonlinearities. An Absolute Limit Switch (MFS-32192-1) utilizes the SCAPS technology to produce an absolute limit switch point, such as to stop a movable carriage. The system for sensing the position of a rotor in a hybrid stepper motor (MFS-32402-1) is a rate-insensitive (i.e., operates at any speed, including zero rate), linear feedback sensor system that can be used for controlling two-phase and multi-phase stepper motors. The Micro-Commanding Servo Motor Controller With Greater Than Fifty Million To One Dynamic Rate Range technology (MFS-31529-1) senses rotary position of a drive shaft to derive appropriate drive signals for a motor. The Short-Range Antenna/Close-Proximity Transmitter and Receiver technology (MFS- 32228-1) is an inexpensive and effective method of exchanging information over a short distance between two devices when each is equipped with a SCAPS coil.
Conductive Oxides
Conductive High-Toughness Oxides
Oxide coatings have been used in thermal and environmental barrier layers for coatings for hot section turbine applications, among other uses. With the PS-PVD method, Glenn researchers observed the formation of a minority phase of a metastable oxide (zirconium oxide) that is usually found only in a vapor state. They found that the high temperatures and fast deposition process of the PS-PVD system incorporated nonequilibrium phases in the coating and retained them at room temperature as well as at high temperature in the absence of oxygen. The material is vaporized and condensed on the surface via a rapid quenching, essentially &#34trapping&#34 this phase in the deposited coating. The coating microstructure and composition can also be manipulated by changing the processing parameters, allowing the thickness of the coating to be tailored to a given application. Since this metastable phase is conductive, this coating can be used as (for example) an extremely sensitive (thermal or temperature) sensor. It also has very good durability and erosion resistance, making it useful as a protective and conductive coating for electronics and microelectronics. This is an early-stage technology requiring additional development, and Glenn welcomes co-development opportunities.
Control of Carbon Nanotube (CNT) Density & Tower Height in a an Array
Control of Carbon Nanotube (CNT) Density & Tower Height in an Array
This method provides control over the growth density or tower height of carbon nanotubes (CNTs) on a relatively coarse scale, with density adjustment over several orders of magnitude, using an applied electrical field or voltage difference that is aligned substantially perpendicular to the substrate surface, which is adjacent to the surface during growth. Control or influence of CNT growth density on a finer scale, estimated at a factor of 2 to 10, is provided using temperature control for the CNT growth process. For example, an application of a modest electrical field of between 5 and 20 volts over a transverse electrode- to-electrode gap of about 25 m (electrical field value |E|=(28) x 103 volts/cm) is estimated to change CNT growth density by 1 to 3 orders of magnitude (coarse scale); and variation of CNT source average temperature between 700 degree C and 850 degree C is estimated to change CNT growth density by a multiplicative factor of 2 to 10 (fine scale). A first region may have a first range of CNT densities, and an adjacent region, spaced apart from the first region, may have a second range of CNT densities that partly overlap, or has no overlap at all, with the density range of the first region. The second region has a higher CNT density, and uses variable heating and/or a reduced electrical field to provide the higher CNT density based on an experimentally determined growth curve and experimental configuration of a device. This approach should be distinguished from masking of regions on a substrate, where the result is binary where either a CNT array with a fixed density appears, or no CNTs appear in that region at all. The all-or-nothing approach is fine if the goal is thermal transport because maximum thermal transport benefits if the CNT concentrations are as high as possible. However, if the need is for electron transport (e.g., between adjacent signal processing components on a semiconductor chip), the desired CNT density may lie in an intermediate range, with both a lower bound and an upper bound.
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