Analog Signal Correlating

Each of two analog signals (channels A and B) is converted to a digital bit stream by phase correcting it and comparing it to an average of itself at a sampling clock rate f. The hard-limited conversions of A and B are bitwise compared to measure the level of similarity between the two by the OBDC. This similarity measurement X is equal to the maximum possible Hamming distance (N bits in disagreement) minus the measured number of bits in disagreement. The OBDC functions are embedded into a field programmable gate array (FPGA). The OBDC is made up of two shift registers containing the current sample values (of length N) from each of the two input channels (A and B). During each sample clock, a new sample from each A and B input is clocked into the input linear shift register for each respective channel; this input shifts the current values in the linear shift register. Once the inputs have been clocked in, the correlation routine can start. Once the correlation value has been calculated, this result is forwarded to compare with the max correlation value register. If the X value is greater than the current max correlation value, then the max correlation value becomes X, and the shift counter register is latched and put into the best correlation index register, providing the index of the current best correlation. This index is the number of sample clock periods difference between the two input signals and thus, for sample clock rate f, indicates the delay between the signals A and B. This is an early-stage technology requiring additional development. Glenn welcomes co-development opportunities.